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Oct 15, 2007
Physical Design (Layout) Engineer, Qimonda North America
DESCRIPTION: You will have a close partnership with the Design Team to complete a variety of physical design assignments that meet the requirements of the engineered schematics and physical design rule criteria, including the verification of the layout using industry standard tools (LVS, DRC). You will convert schematic descriptions into optimized floor planning and topology as well as structured block layout for state of the art low power DRAM s. Your primary focus is on full custom physical design; from global floor planning to individual circuit block layout (analog and digital). REQUIREMENTS: In accomplishing these assignments, the engineer must have the following skills: A Bachelor\'s degree or equivalent technical industry experience in full custom layout is required. The candidate must be effective in teams, have a high awareness of project details, and demonstrate strong problem solving skills. A familiarity with industry standard DRC and LVS tools (Cadence, Mentor Graphics) is required. Experienced candidates should have at least 3 years of transistor level full custom layout and floor planning. Experience with DRAM, SRAM and/or Pseudo-SRAM design and CMOS IC mask design methodologies is a plus.
Company name: Qimonda North America · Location: Williston, VT,
Company name: Qimonda North America · Location: Williston, VT,